bbf7d3aa14
Experimentally drop the HGAIN to x8. Currently the evidence base for this change is a little weak but it doesn't seem to be *worse* than what we have now. Therefore I hope the wasp-os users will forgive me for using them as guinea pigs! Signed-off-by: Daniel Thompson <daniel@redfelineninja.org.uk>
98 lines
2.4 KiB
Python
98 lines
2.4 KiB
Python
# SPDX-License-Identifier: LGPL-3.0-or-later
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# Copyright (C) 2020 Daniel Thompson
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"""HRS3300 driver
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~~~~~~~~~~~~~~~~~
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"""
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from micropython import const
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_I2CADDR = const(0x44)
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_ID = const(0x00)
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_ENABLE = const(0x01)
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_ENABLE_HEN = const(0x80)
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_C1DATAM = const(0x08)
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_C0DATAM = const(0x09)
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_C0DATAH = const(0x0a)
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_PDRIVER = const(0x0c)
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_C1DATAH = const(0x0d)
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_C1DATAL = const(0x0e)
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_C0DATAL = const(0x0f)
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_RES = const(0x16)
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_HGAIN = const(0x17)
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class HRS3300:
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def __init__(self, i2c):
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self._i2c = i2c
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def init(self):
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w = self.write_reg
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# HRS disabled, 12.5 ms wait time between cycles, (partly) 20mA drive
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w(_ENABLE, 0x60)
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# (partly) 20mA drive, power on, "magic" (datasheet says both
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# "reserved" and "set low nibble to 8" but 0xe gives better results
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# and is used by at least two other HRS3300 drivers
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w(_PDRIVER, 0x6e)
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# HRS and ALS both in 16-bit mode
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w(_RES, 0x88)
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# 64x gain
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#w(_HGAIN, 0x10)
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w(_HGAIN, 0x03)
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def read_reg(self, addr):
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return self._i2c.readfrom_mem(_I2CADDR, addr, 1)[0]
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def write_reg(self, addr, val):
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self._i2c.writeto_mem(_I2CADDR, addr, bytes((val,)))
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def enable(self):
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self.init()
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enable = self.read_reg(_ENABLE)
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enable |= _ENABLE_HEN
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self.write_reg(_ENABLE, enable)
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def disable(self):
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enable = self.read_reg(_ENABLE)
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enable &= ~_ENABLE_HEN
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self.write_reg(_ENABLE, enable)
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def read_hrs(self):
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# TODO: Try fusing the read of H & L
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m = self.read_reg(_C0DATAM)
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h = self.read_reg(_C0DATAH)
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l = self.read_reg(_C0DATAL)
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return (m << 8) | ((h & 0x0f) << 4) | (l & 0x0f) | ((l & 0x30) << 12)
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def read_als(self):
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# TODO: Try fusing the read of H & L
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m = self.read_reg(_C1DATAM)
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h = self.read_reg(_C1DATAH)
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l = self.read_reg(_C1DATAL)
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return (m << 3) | ((h & 0x3f) << 11) | (l & 0x07)
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def set_gain(self, gain):
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if gain > 64:
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gain = 64
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hgain = 0
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while (1 << hgain) < gain:
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hgain += 1
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self.write_reg(_HGAIN, hgain << 2)
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def set_drive(self, drive):
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en = self.read_reg(_ENABLE)
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pd = self.read_reg(_PDRIVER)
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en = (en & 0xf7) | ((drive & 2) << 2)
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pd = (pd & 0xbf) | ((drive & 1) << 6)
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self.write_reg(_ENABLE, en)
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self.write_reg(_PDRIVER, pd)
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